Captain Mingdos

128MB  for every bank. Total  8 memory banks . Six memory banks for ROM, SRAM , etc. Remaining  two memory banks for ROM, SRAM, SDRAM , etc . There are  7 banks with fixed start address . The  size  and  start address  of  bank7  can  change , while the  size of bank6 is changeable (equal to the size of bank7) , but with  fixed start address . The memory mapping is shown below: From picture above, we can see: Although S3C2440 is a 32-bit chip which  theoretically  means the chip can have a maximum memroy 4GB, but in fact  it only has 1GB memory to use for data and code . A s for the remaining 3GB, some of which is used for special registers, and the others is not used (it is kind of waste, isn't it!) . The  start address and size of bank7 is changeable , but the  sizes of bank6 and bank7 have to keep the same . So the  size of bank6 is also changeable , but with  fix...

[1]"A module can contain any combination of following:  net/variable declarations(wire, reg, integer, etc.) ,  concurrent and sequential statement blocks , and  instances of other modules(subhierarchies) .  Sequential statements  are placed inside a  begin/end block  and  executed in sequential order  within the block. But  the blocks themselves are executed concurrently , qualifying Verilog as a data language." [2]"There is no need to explicitly declare wires; any undeclared identifiers default to wires. Note: undeclared wires must by single bit." "All  continuous assignments  are active concurrently." "In Verilog we use  procedural blocks  to model  edge-triggered  behaviour." "An always block can be used to describe both  combinational  and  sequential  hardwire." " All blocks in the design execute concurrently ." [5] " assign声明 只能用在 组合逻辑电路(combinational logic)...

Package on package design Package on package (PoP) is an integrated circuit packaging method to combine vertically discrete logic (like processors) and memory ball grid array (BGA) packages which is used in A5 chip by iphone.There is a standard interface to route signals between different packages. It is shown as following: Two widely used configurations exist for PoP: 1. Pure memory stacking - two or more memory only packages are stacked on each other 2. Mixed logic-memory stacking - logic (CPU) package on the bottom, memory package on top. For example, the bottom could be an application processor for a mobile phone. The logic package (processors) is on the bottom because it needs many more BGA connections to the motherboard. Benifits: 1), Mother space saving Minizing track length between different interoperating parts, such as a controller and a memory. 1), faster signal propagation 2), reduced noise and cross-talk Memory is decompled from logic device....

Byte Alignment , actually is designed for realizing   the convenience of memory addressing , to   improve the speed of addressing . To understand it, we gonna talk about the difference between using Byte Alignment and non-Byte Alignment: struct A {      char c;      int i;  };  struct A a; We use the structure above to explain the function of Byte Alignment. Without Byte Alignemnt, the address of variable c is 0x00, and the address of i is 0x01. If   the addressing scope  of cpu is 4 bytes , we will   need two read cycles to get i . Variable c need a read cycle to be read, however   variable i need two read cycle to be read because there are three bytes of i in 0x01, 0x02, 0x03 which are read in the variable c read cycle . So   when the cpu read the 0x04, it has to connect the three bytes 0x01, 0x02, 0x03 . As we see, we need two read bytes to get i, it is low efficient. However, ...

Synchronous and Asynchronous(in hardware communication) Synchronous :   different hardwares   must use the   same clock signal . For example,   SPI   protocol require the Master and Slave have to use the same clock signal which comes from Master. Asynchronous :   different hardwares   can use   different clock signal( the baudrate should be the same) . For example,   UART   transmits data with   8 bits   which contains   start bit   and/or   stop bit   used to verify if the data transmit is correct because of the   different clocks they use . Please refer to the   artile on 1st April 2011 . Serial Interfaces SPI(Serial Peripheral Interface)   is a serial interface standard. Basically, SPI need four pins which are:   cs, clk, so and si . And most of SPI use   Master-Slave   mode to work. cs : used to select the Slave chip. There is nothing to say about this par...

Build a project:  Project -> Create New Project . After create a project, you can programm C code in file window. When you finish programming, you need to  configure the project first . Open project option:  Project -> Options . In the  General Options  category, you can configure  t he type of Processor Core or Chip Device . And click the third tab  Code  under  sub category  C/C++ Compiler , you can set the  Processor mode: Arm or Thumb . In the  Debugger  category, you can set the Diver for  Simulator ,  J-Link ,  J-Trace ,  Third-Party Driver  or something else. If the Driver above, you choose Third-Party Driver, then in  Debugger -> Third-Party Driver , you can choose the path of the Third-Party Driver. After the configuration, you can compile and make the C code. Then  click the button "Download and Debug" , must  beware not "Debug with...

Startup in linux: 1, In linux, file /etc/init.d/rc.local is the startup file of linux. So if you want to start some commend when the system boot, you can write the commend or script at the end of the file. 2, If you want to mount some disk, first you need to be sure the disk wasn't mounted on some place else. Otherwise, you need to unmount the dev file before the mount the file on the target.

Lex 与 Yacc      其实，在我看来lex和yacc就是一套 文字识别及语法分析 的编程软件，它们基于 宿主语言(host languge) 进行编程，例如常用的宿主语言有 C 、 C++ 和 basic 。但是它们在自己的 规则部分 (也就是文件的第二部分)都有相应的语法规则，例如lex用 正则表达式(regular expression) 实现词法识别，词法识别实际上就是把输入文件中字符进行 归类 (例如 关键字 、 变量 、 立即数 等)，将其归类为不同的tokens。这里还涉及到一个概念那就是terminals。在这里 terminals和tokens是同义词 ，表达的是一个含义，都是 不能再分割的基本单元 。这里不能再分割指的就是区别于 yacc中可以再分割的nonterminals ， 因为yacc中规则部分实际上就是利用递归(recursion)来进行语法识别 。 yacc用nonterminals不断地递归下一层的nonterminals或者terminals，直到所有的最底层的语法都用terminals来表述，即不能再分割 。 terminals 用 大写字母 表示， nonterminals 用 小写字母 表示。这里先做简单介绍，后面会有详细的讲解。 1.如何编译和执行Lex与Yacc源代码？      例如有lex和yacc的源代码分别为example.l和example.y。如果宿主语言是C语言的话(以下未特殊说明，均指C语言)，由于 lex和yacc的源代码规则部分都不是C语言 ，所以 不能直接拿来用GCC编译 ，所以我们要先 用lex和yacc指令来将源代码转换成完整的C语言文件 。如下：      lex example.l      yacc -d example.y      第一条指令执行后生成lex.yy.c的C程序文件。第二条指令因为使用了 option -d ，所以 该条指令生成两个文件，分别是y.tab.c和y.tab.h 。这里y.tab.h里面包含的是 各个token的宏定义 ，从 257 开始给每个to...