ARM memory management (Chip S3C2440 with Core ARM920T)

1. 128MB for every bank.
2. Total 8 memory banks.Six memory banks for ROM, SRAM, etc.Remaining two memory banks for ROM, SRAM, SDRAM, etc .
3. There are 7 banks with fixed start address.
4. The size and start address of bank7 can change, while the size of bank6 is changeable (equal to the size of bank7), but with fixed start address.

The memory mapping is shown below:

From picture above, we can see:

1. Although S3C2440 is a 32-bit chip which theoretically means the chip can have a maximum memroy 4GB, but in fact it only has 1GB memory to use for data and code. As for the remaining 3GB, some of which is used for special registers, and the others is not used (it is kind of waste, isn't it!).
2. The start address and size of bank7 is changeable, but the sizes of bank6 and bank7 have to keep the same. So the size of bank6 is also changeable, but with fixed start address.
3. Usually, the bank6 and bank7 are used for SDRAM, so basically bank6 and bank7 is used for RAM. So the maximun of RAM of S3C2440 chip is 256MB.

Memory organization with S3C2440 application:

I will talk about memory organization according to board TQ2440 which is bought from China. The specification of core board is:

• S3C2440 CPU
• 64MB SDRAM
• 2MB Nor flash
• 512MB Nand flash

There are three kinds of memory chip can be used with S3C2440: SDRAM, Nor flash and Nand flash. We can choose Nor flash or Nand flash as the working ROM though pins OM1 and OM2 like the table below.

S3C2440 chip uses address pins LADDR0-LADDR26 (128MB) and banks selection pins nGCS0-nGCS7 to locate the certain memory units. So when the chips try to decode the PC register, there are two decoding modes:

ROM: nGCS pin + address pins

RAM: nGCS pin + address pins (Multplexing)

SDRAM connections:

Here we talk about SDRAM first, which uses multiplexing addressing mode to access memory units. Two 32MB 16-bit width SDRAM chips is used together to form 64MB RAM which has 32-bit data width. 

From the schematic above, we can see:

1. The address pins are multiplexing pins: A0-A12 for rows, A0-A8 for columns.
2. BA0-BA1 are used for selecting the internal banks of SDRAM.
3. The memory system is 4-byte alignment. So the address pins are used from LADDR2, LADDR0 and LADDR1 are not used.
4. nSCS is the chip selection pin connected with nGCS6 pin of S3C2440, which means SDRAM working in address space 0x30000000.

Here we can calculate how we get the 64MB RAM like below:

2^(13(A0-A12)+9(A0-A8)+2(BA0,BA1))*16 bit*2 chip = 64MB

Nor flash connections:

Nor flash is an XIP (executed in place) memory. It uses linear addressing mode which make the addressing is the easiest.

From the schematic above, we can see:

1. There are 20 address pins (A20 and A21 are not used).
2. The data width is 16-bit, so the address pins are used from LADDR1. Does this mean we have to only store the THUMB instructions which are 16-bit size in this kind of Nor flash?
3. Here the chip selection pin is connected to the pin nGCS0 of S3C2440 chip, which means it will work in address space 0x00000000.

The 2MB size of Nor flash can be calculated like below:

2^20(A0-A19)*16bit = 2MB

Internal SRAM:

S3C2440 chip has its own internal SRAM whose size is 4KB. This is far enough from storing the kernel of operating system and it is volatile. So we have to use externel memories.

When we use Nand flash mode (OM(1,0) = 00), the 4KB SRAM is mapped to address 0x00000000, now it is called "Steppingstone", so that it can load the boot program.

When using Nor flash mode (OM(1,0) = 10 or 01), the SRAM mapping is changed into address 0x40000000, because Nor flash is mapped to 0x00000000 to boot program in Nor flash.

Anyway, when the system resets, the program is always executed from address 0x00000000.

Summary:

The memory location of board TQ2440 is:

0x00000000->0x001FFFFF                                                         2M Nor flash

0x30000000->0x33FFFFFF                                                         64M SDRAM

0x00000000->0x00001000 or 0x40000000->0x40001000          4K Internal SRAM

0x48000000~                                                                                Special registers

As for Nand flash, which can be regarded as the normal peripherals whithout mapping in address space of S3C2440. So here Steppingstone is coming. When the system resets, the first 4KB in Nand flash is carried into the Steppingstone by Nand flash controller. The 4KB bootloader program loads the kernel of operating system into the SDRAM which is mapped to 0x30000000.

We can see the design of Steppingstone in S3C2440 is sweet. Without Steppingstone, we have to use an extra Nor flash to store the bootloader code which can load the kernel image of operating system. Now with Steppingstone, we can save both bootloader code and kernel image in Nand flash.

References:

[1] S3C2440 datasheet, Sumsung

[2] S3C2440存储控制器和MMU浅析, http://blog.csdn.net/ayangke/article/details/6880846

[3] TQ2440学习笔记-裸奔程序流水灯, http://www.dpj365.com/blog/?tag=%E7%AC%94%E8%AE%B0