Verilog杂七杂八

[1]"A module can contain any combination of following: net/variable declarations(wire, reg, integer, etc.), concurrent and sequential statement blocks, and instances of other modules(subhierarchies). Sequential statements are placed inside a begin/end block and executed in sequential order within the block. But the blocks themselves are executed concurrently, qualifying Verilog as a data language."

[2]"There is no need to explicitly declare wires; any undeclared identifiers default to wires. Note: undeclared wires must by single bit."

"All continuous assignments are active concurrently."

"In Verilog we use procedural blocks to model edge-triggered behaviour."

"An always block can be used to describe both combinational and sequential hardwire."

"All blocks in the design execute concurrently."

[5] "assign声明只能用在组合逻辑电路(combinational logic)中，不能用在always block中，即时序逻辑电路中(sequential logic)。"

reg vs wire:

[2]

reg signals can be connected to the input port of a module instance used as outputs in a module declaration assigned to in an always @ block using <= or = assigned to in an intial block (later) used to create registers in an always @ (posedge clk) block used for both sequential and combinational logic	wire signals can be used to connect inputs and outputs of module instances used as inputs and outputs in module declaration can be assigned to with an assign statement used to model only combinational logic
reg signals cannot be connected to the output ports of a module instance used as inputs in a module declaration used on the left side of an assign statement	wire signals cannot be used on the left side of a <= or = assignment in an always block used to model sequential logic

     从上面的资料我们可以看出，wire一般用于blocks外面的线连接，仅仅是用来连接的，所以其没有记忆功能。而reg一般使用在blocks中像变量一样使用(也可以在blocks外面使用)，配合着<=，可以实现状态间的数据传输，实现系统的记忆性。例如：

     always @ (posedge clk)

     begin

          q1<=in; 

          q2<=q1;

          out<=q2;

     end

     两个clock状态，前一个clock的数据能保留到当前clock的原因就是因为in, q1, q2都是reg类型。

     下面是一段来自百度百科对wire和reg不同较为准确地讲解:

     [4]"Verilog里一般不声明输出类型的话  默认是wire型的如果你想在输出处寄存一下：比如使用always语句，则必须声明为reg类型。wire是线网，就是相当于实际中的连接线，你想assign的话就是直接连接，就是用wire型，它的值是随时变化的。比如你想寄存一下，让他在时钟边沿才变化就需要reg类型了"

begin/end and fork/join

begin/end块内的语句都是顺序执行的，就像软件程序一样儿，当然要除去使用nonblocking "<="的情况。nonblocking的部分先同时计算"<="右边的部分，然后在遇到end的时候同时放到"<="左边的reg中。[6]

begin/end和fork/join可以互相嵌套。

Blocking and Nonblocking

Nonblocking "<=" :

"<=" 右边所有的表达式先计算，直到所有的计算都完成后(遇到end from "begin/end")，才将右边所得的所有计算结果assign到左边的register中。

用在sequential logic中。

实际上主要用于Flip-Flop circuit。

Blocking "=":

"=" 计算完立即放入左边，每一个式子都是这样。

用在combinational logic中。

Combinational logic(组合逻辑电路): 即，有输入就立即产生当前状态下的输出。没有任何"记忆性"。

Sequential logic(时序逻辑电路): 即，输出与过去的输入有关，所以系统具有"记忆"功能。

References:

[1] "Verilog Wikipedia", http://en.wikipedia.org/wiki/Verilog

[2] "2 - IntroVerilog Lecture", NTU embedded systems lectures

[3] "Blocking vs Nonblocking Assignments.pdf", in Dropbox

[4] "verilog变量reg和wire问题", 百度百科 http://zhidao.baidu.com/question/262629908.html?fr=qrl&cid=866&index=3

[5] "Verilog中的assign以及always", 百度百科 http://zhidao.baidu.com/question/358599023.html

[6] Procedual blocks: begin-end and fork-join http://electrosofts.com/verilog/beginend.html