Digital system design flow

Specification:

We need to define the requirements and implementation constraints of our system like we design a software architecture. 

High-Level Design:

We need to define the top-level architecture, which includes the modules needed in the design and how they communicate with each other.

Low-Level Design:

Each module in this stage should be implemented using simple design components like memories, regsisters, state machines, etc.

HDL Coding:

Here we need to use HDL to write code to implement the low-level design. Here HDL code must be synthesisable.

Functional Simulation:

Here we use the software simulator to test if the HDL design does the right things which are required by the specification.

Synthesis:

After the simulation verified the design complete the requirement by specification, then map the HDL design to the target technology primitives, initial timing info is obtained.

Placement & Routing:

Here all the primitives in the synthesised netlist are mapped to a location on the target. Then connect the inputs and outputs to pins of FPGA. (passing of signals, clock trees are generated detailed timing information is obtained)

Tming Simulation:

After synthesis, you need to simulate the target again to chech that if the whole design meets the timing constraints set in the specification.

Fabrication:

For FPGA design, now all the works have been done. For an ASIC, mask sets are produced and silicon wafers are etched.

Post Silicon Validation:

After the chip is manufactured, we are supposed to test it in field conditions again. If there are bugs here, then all the chips become rubbish.