Only 56 instructions in ARM Cortex-M0

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16-Bit Thumb Instructions Supported on the Cortex-M0 Processor

ADC      ADD        ADR     AND     ASR     B           BIC        BLX          BKPT     BX
CMN     CMP        CPS      EOR     LDM     LDR     LDRH     LDRSH     LDRB     LDRSB
LSL        LSR         MOV    MVN    MUL    NOP     ORR       POP          PUSH     REV
REV16   REVSH    ROR     RSB      SBC     SEV      STM       STR          STRH      STRB
SUB       SVC         SXTB   SXTH   TST      UXTB   UXTH    WFE         WFI         YIELD


32-Bit Thumb Instructions Supported on the Cortex-M0 Processor

BL     DSB     DMB     ISB     MRS     MSR

The instructions in the Cortex-M0 processor can be divided into various groups based on functionality:
  • Moving data within the processor (MOV  MRS  MSR)
  • Memory accesses (LDR  LDRH  LDRB  LDRSH  LDRSB  STR  STRH  STRB  LDM  STM)
  • Stack memory accesses (PUSH  POP)
  • Arithmetic operations (ADD  ADR  SUB  ADC  SBC  RSB  MUL  CMP  CMN)
  • Logic operations (AND  ORR  EOR  BIC  MVN  TST)
  • Shift and rotate operations (ASR  LSL  LSR  ROR )
  • Extend and reverse ordering operations (REV  REV16  REVSH  SXTB  SXTH  UXTB  UXTH)
  • Program flow control (branch, conditional branch, and function calls) (B  BL  BX  BLX)
  • Memory barrier instructions (DMB  DSB  ISB)
  • Exception-related instructions (SVC  CPS)
  • Sleep mode feature-related instructions (WFI  WFE  SEV)
  • Other functions (NOP  BKPT  YIELD)

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